1. Field of the Invention
The invention includes error detection/correction and fault detection/recovery. More particularly, the invention includes digital logic testing through a reduction in the number of global test control lines.
2. Background Information
An integrated circuit or “chip” is a microelectronic semiconductor device having many interconnected transistors and other components. Chips may be fabricated on a small rectangle cut from a silicon wafer. The small size of these circuits allows high speed, low power dissipation, and reduced manufacturing cost compared with board-level integration.
The first integrated circuits contained only a few transistors. Small Scale Integration (SSI) brought circuits containing transistors numbered in the tens. Later, Medium Scale Integration (MSI) contained hundreds of transistors and Large Scale Integration (LSI) contained thousands of transistors. At present Very Large Scale Integration (VLSI) circuit chips are composed of hundreds of thousands of logic elements or memory cells. Digital VLSI integrated circuits may contain anything from one to millions of logic gates—inverters, gates, flip-flops, and multiplexors on a few square millimeters.
Part of producing a scaleable VLSI chip includes testing and debugging the chip. Debugging is an attempt to determine the cause of any malfunction symptoms detected by testing. Circuitry may be built into an integrated circuit to assist in the test, maintenance, and support of an assembled circuit. Hardware features, known as design for test (DFT) features or resources, may be incorporated into a chip to aid in testing and debugging.
Determining the cause of a malfunction or other problem may be achieved by using a testing machine to send a simulated signal from a debug pin residing on the perimeter of the chip to a logic element within the chip so as to trigger a response bit (0 or 1) from that logic element. On a clock signal, an instruction may cause a snapshot or “scan” to be taken of this triggered response bit by a DFT feature. On the next clock signal, and as part of that same instruction, the scan information bit may be shifted one bit “out” towards a serial output the chip to a second perimeter pin so that the scan bit may be compared to an expected response. If this triggered response or “scanout” varies from the expected response, then that particular logic element may be a cause of the noted problem.
To adequately debug a chip, it may be necessary to view a sampled state of hundreds of chip-internal signals within a space of minutes. Conventionally, a first debugging technique may be used to isolate a probable bug location from a million transistors to a group of a few hundred transistors. Then, a second debugging technique may be used to rapidly find the exact transistor failure point from the grouped few hundred transistors. Chips may have redundant transistors in them such that, once a transistor failure point is located, the transistor may be turned off as part of chip production while a redundant transistor may then similarly be turned on.
To isolate a probable bug location from a million transistors to a group of a few hundred transistors, an integrated circuit chip may be designed to include internal read-only test points. These test points (or scanout “cells”) generally are scattered throughout the integrated circuit chip. When chained together to form a distributed shift register, scanout cells produce parallel data that provides observability of selected nodes during functional testing during normal operation of the chip.
U.S. Pat. No. 5,253,255 teaches a centralized control mechanism that employs two global test control lines for each design for test (DFT) feature. Here, sequentially activating the snapshot and the shift with signals requires two global speed critical signals that require close timing tolerances between the two signals.